This invention relates to memory modules, and more particularly to buffering signals on memory modules.
Memory modules such as dual-inline memory modules (DIMMs) are widely used in electronic systems such as personal computers (PCs). Memory modules have memory chips such as dynamic-random-access memories (DRAMs) mounted on a small substrate such as a printed-circuit board (PCB). Contact pads are formed along one edge of the substrate to make electrical contact when the memory module is plugged into a socket such as on a PC motherboard.
As these electronic systems operate at higher and higher speeds, signals driven to the memory modules must also operate at higher frequencies. Faster high-current drivers can be used to more rapidly drive current to charge and discharge the capacitances on the inputs of DRAM chips on the memory modules. These DRAM-input capacitances can be significant, producing a large capacitive load on the inputs to the memory modules, especially when many DRAM chips are mounted on the same memory module.
Further compounding the input-capacitance problem is the use of expansion memory. A PC motherboard may contain several memory-module sockets such as 2 or 4. Initially, only one socket may be populated with a memory module, but later the end-user may insert additional memory modules into the unused memory-module sockets to expand the memory capacity. Input capacitance can double or quadruple when the end-user installs additional memory.
FIG. 1 shows a signal trace on a typical memory module. Chip set 10 on a PC motherboard includes driver 12 that drives line 14. Line 14 is the address line A0, but could be other address or control lines generated by a memory controller. Line 14 is routed from chip set 10 along wiring traces on the multi-layer PC motherboard to one or more memory module sockets, including a socket containing DIMM 20.
Contact pads along an edge of DIMM 20 make electrical contact with metal tabs inside the memory module socket. One of the contact pads connects line 14 on the PC motherboard to line 16 on DIMM 20. Line 16 is a wiring trace on or within the memory module substrate of DIMM 20.
DIMM 20 contains eight DRAM chips 21-28. DRAM chips 21-28 can be synchronous DRAMs (SDRAMs) that receive a clock as one of the control lines. Some DIMM modules may have fewer or more DRAM chips than the 8 shown in this example.
The A0 address signal must be routed to inputs of all 8 DRAM chips 21-28. Line 16 is initially one trace, but then branches into two branches at junction A. One branch continues to junction B1, where it again splits, ultimately to four branches C1, C2, C3, C4 that connect to inputs of DRAM chips 21-24. The lower branch continues to junction B2, where it again splits, ultimately to four more branches C5, C6, C7, C8 that connect to inputs of DRAM chips 25-28.
FIG. 2 highlights a reflection problem caused by trace junctions. Line 14 from the PC motherboard enters the memory module through the socket and follows a metal wiring trace on the memory module substrate until junction A. This input trace has an impedance determined primarily by its width, thickness, and length, and proximity to other wiring traces and layers. Often minimum-width wiring traces are used for all signal traces on the memory module, although power and ground may use wider traces.
The input trace, using the minimum trace width, has a characteristic impedance of about 60 ohms. The branch from junction A to junction B1 also uses the minimum width, and also has an impedance of 60 ohms. The final stubs to the inputs of DRAM chips 21-28 are very short but usually have the same impedance, about 60 ohms.
When the driver on the chip set drives the signal to the opposite state, and initial wave-front or surge of current i travels down line 14 toward junction A. At junction A, the current is split into two halves or roughly i/2 each. At junctions B1, B2, the current is again divided. Since wiring traces have the same impedance before and after junction A, the initial voltage from the initial wave-front traveling along the branch to B1 is half the voltage before junction A, since VA=i*ZA before junction A, and VB=i/2*ZB along each branch after junction A. When impedances ZA before A and ZB after A are the same, then VB=VA/2.
Of course, these are rough estimates, and actual impedances will not be exactly equal, and the voltage drop-off after junction A may not be exactly 50%. However, the general idea is that the instantaneous voltage of the initial wave-front drops off after junction A when the same-width and same-thickness wiring traces are used before and after the junction.
Further voltage reduction of that initial wave-front can occur at junctions B1, B2, and further reduce the initial voltage applied to the inputs to DRAM chips 21-28. Reflections can also occur at the junctions and from the chip inputs.
As higher frequencies are used, wiring traces act more like transmission lines. Reflections from junctions and chip inputs travel backward along the line after the initial wave-front reaches the junctions or chip inputs. These reflections disturb instantaneous voltages along the line, and take time to settle. This settling time can reduce the practical operating frequency.
Termination circuits such as resistors are normally added to trace endpoints on other systems, but memory modules are so small that such terminations are not practical.
FIG. 3 is a timing diagram showing the problem of voltage drop-off at trace junctions on the memory module. The chip set may drive signal A0 high in response to a rising edge of clock CK. After some delay from the clock, the driver drives an initial wave-front down the trace to the memory module. The voltage at the chip inputs C2, C3,â is shown. Voltage drop-offs at junctions A and B1 reduce the voltage of the initial wave-front, and cause reflections that reduce the voltage at C1, C2, such as knee 32 caused by junction A, and knee 34, caused by junction B1.
The delay until the voltage at DRAM inputs C2, C3 rises above the logic threshold is the propagation delay. This propagation delay is extended due to knee 32. The logic threshold of the DRAM input is not reached by the initial wave-front. Instead, the voltage rises above the logic threshold only after one or more reflections return and then boost the voltage above the logic threshold.
What is desired is a memory module with improved wiring-trace design to reduce signal propagation delays. Wiring traces that have an intentional impedance-step are desired to reduce junction reflections and improve speed. It is desired to reach the DRAM logic threshold voltage on the initial wave-front to reduce delays due to transmission-line effects.